A major concern for advanced dynamic RAMs (DRAM) has become test time reduction. Previous DRAMs could achieve relatively efficient test time reduction through design for test (DFT) schemes, because the number of parallel bits to be tested was on the same order in size as the maximum word size. For example, the 4MB DRAM is capable of .times.8 and .times.16 parallel test, because 16 bits are available from the array on each read cycle. For the 16MB DRAM, .times.16 and .times.32 parallel tests are possible, but the .times.32 requires that an additional array of memory cells and amplifiers be enabled in order to read 32bits from the array in one cycle. The enabling of an additional array of memory cells and their corresponding amplifiers is a problem because the total power required to enable the additional array in conjunction with the enabled arrays for the .times.16 test exceeds, in most situations, the power required during normal usage (and may even exceed the maximum power limit for the memory device). The problem becomes much more difficult for the 64MB (and greater) DRAM, where .times.64 parallel test is a minimum requirement and access time and silicon area are critical considerations.